Threshold Voltage Design of UTB SOI SRAM With Improved Stability/Variability for Ultralow Voltage Near Subthreshold Operation
In: IEEE Transactions on Nanotechnology, Jg. 12 (2013-07-01), S. 524-531
Online
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Zugriff:
This paper analyzes and compares the stability, margin, performance, and variability of ultrathin-body (UTB) SOI 6T SRAM cells operating near the subthreshold region with different threshold voltage (Vth) design. Our results indicate that UTB SOI 6T SRAM cell using low Vth devices (|Vth| = 0.19 V) shows a comparable read static noise margin (RSNM), 41% improvement in σRSNM, 84% improvement in write static noise margin (WSNM), and 67% improvement in σWSNM as compared with the case using higher Vth devices (|Vth| = 0.49 V). As Vth decreases (work function moves to the band edge), the “cell” access time improves significantly with correspondingly higher standby leakage. For low Vth devices (|Vth| = 0.19 V), it is shown that lowering bit-line precharge voltage by 50 mV reduces the standby leakage by 20%. Our study suggests that the lower Vth devices operating slightly into super-threshold region improve the stability/variability significantly and offer higher performance for ultralow voltage SRAM applications.
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Threshold Voltage Design of UTB SOI SRAM With Improved Stability/Variability for Ultralow Voltage Near Subthreshold Operation
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Autor/in / Beteiligte Person: | Chuang, Ching-Te ; Fan, Ming-Long ; Su, Pin ; Vita Pi-Ho Hu |
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Zeitschrift: | IEEE Transactions on Nanotechnology, Jg. 12 (2013-07-01), S. 524-531 |
Veröffentlichung: | Institute of Electrical and Electronics Engineers (IEEE), 2013 |
Medientyp: | unknown |
ISSN: | 1941-0085 (print) ; 1536-125X (print) |
DOI: | 10.1109/tnano.2011.2105278 |
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