Sub-25nm UTB SOI SRAM cell under the influence of discrete random dopants

Intrinsic parameter fluctuations steadily increase with CMOS technology scaling. Around the 65 nm technology node, such fluctuations will eliminate much of the available noise margin in SRAM based on conventional MOSFETs. Device mismatch due to intrinsic parameter fluctuation causes each memory cell of the millions in a typical memory array to have different stability and performance. Ultra Thin Body (UTB) SOI MOSFETs are expected to replace conventional MOSFETs for integrated memory applications due to superior electrostatic integrity and better resistant to some of the sources of intrinsic parameter fluctuations. Using a statistical circuit simulation methodology which can fully capture intrinsic parameter fluctuation information into compact model, the impact of random discrete doping effects on 6T SRAM cell has been investigated for well scaled UTB SOI devices with physical channel length in the range of 10–5 nm. The impact of random doping in the source/drain regions of UTB SOI devices is quantified by changing the SRAM cell ratio and measuring the stability and performance during read and write operations. A comparison with the static noise margin characteristic of a 6T SRAM based on a conventional 35 nm MOSFET is also presented.