Analysis of Negative Capacitance UTB SOI MOSFETs considering Line-Edge Roughness and Work Function Variation
In: 2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM), 2018-03-01
Online
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Zugriff:
We analyze the threshold voltage (Vt) and switching time (ST) variations of negative capacitance UTB SOI MOSFETs (NC-SOI) and UTB SOI MOSFETs considering line-edge roughness (LER) and work function variation (WFV). Compared to SOI, NC-SOI exhibits smaller LER induced Vt variations (σVt}) and comparable WFV induced Vt variations. LER induced σVt} can be suppressed by negative capacitance, while WFV induced σVt} cannot be suppressed by negative capacitance. For considering LER, NC-SOI with larger subthreshold swing (SS) and worse short channel effect exhibits better capacitance matching, larger voltage gain (Av), and larger threshold voltage difference (Vt NC-SOI -Vt SOI ), which mitigates the σVt}. For NC-SOI MOSFETs, WFV induced σVt} (=16.2mV) is larger than LER induced σVt} (=3.8mV). For SOI MOSFETs, WFV and LER show comparable σVt}. However, for both NC-SOI and SOI MOSFETs, LER induced ST variations are larger than the WFV induced ST variations. This is because transition charge (Δ Q}) and effective drive current (Ieff) are positively correlated for considering WFV and negatively correlated for considering LER. Compared with SOI, NC-SOI considering LER and WFV exhibits smaller ST variations due to larger Ieff.
Titel: |
Analysis of Negative Capacitance UTB SOI MOSFETs considering Line-Edge Roughness and Work Function Variation
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Autor/in / Beteiligte Person: | Chiu, Pin-Chieh ; Vita Pi-Ho Hu |
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Zeitschrift: | 2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM), 2018-03-01 |
Veröffentlichung: | IEEE, 2018 |
Medientyp: | unknown |
DOI: | 10.1109/edtm.2018.8421472 |
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