Interface States Characterization of UTB SOI MOSFETs From the Subthreshold Current
In: IEEE Transactions on Electron Devices, Jg. 68 (2021-02-01), Heft 2, S. 497-502
Online
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Zugriff:
Quantification of interface traps for double-gate fully depleted silicon-on-insulator transistors is needed for accurate device modeling and technology development. The trap density can be estimated as a function of the activation energy from the subthreshold current using the methodology developed in this work. It combines the earlier proposed ${g}_{\text {m}}/ {I}_{\text {D}}$ method with a revised form of the ${k}$ -sweep method. The method is verified using TCAD simulated data and applied on engineering samples produced in 22FDX (R) technology, yielding a typical trap density of ${2}\,\,\cdot \,\,{10}^{{11}}\,\,\text {cm}^{-{2}}\text {eV}^{-{1}}$ . Association of the traps to the front or back interface is nontrivial; a trap allocation error of at least 20% is reported.
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Interface States Characterization of UTB SOI MOSFETs From the Subthreshold Current
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Autor/in / Beteiligte Person: | Vermeer, Matthias L. ; Hoentschel, Jan ; Pirro, L. ; Hueting, Raymond J. E. ; Schmitz, Jurriaan ; Institute, MESA+ ; Integrated Devices and Systems |
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Zeitschrift: | IEEE Transactions on Electron Devices, Jg. 68 (2021-02-01), Heft 2, S. 497-502 |
Veröffentlichung: | 2021 |
Medientyp: | unknown |
ISSN: | 0018-9383 (print) |
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