Optimal UTB FD/SOI device structure using thin BOX for sub-50-nm SRAM design
In: IEEE electron device letters, Jg. 27 (2006), Heft 4, S. 284-287
academicJournal
- print, 17 ref
Zugriff:
In this letter, the random dopant fluctuation effect in ultrathin-body (UTB) fully depleted/silicon-on-insulator (FD/SOI) devices is analyzed. We show that due to larger variability and asymmetry in threshold voltage Vt distribution, it will be difficult to use UTB FD/SOI devices for sub-50-nm static random access memory (SRAM) design. Using thinner buried oxide (BOX) FD/SOI devices, the asymmetry in the Vt spread can be reduced. We present a viable concept of FD/SOI SRAM and predict that a thin-BOX device is the optimal FD/SOI structure for SRAM in sub-50-nm technology nodes.
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Optimal UTB FD/SOI device structure using thin BOX for sub-50-nm SRAM design
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Autor/in / Beteiligte Person: | MUKHOPADHYAY, Saibal ; KIM, Keunwoo ; XINLIN, WANG ; FRANK, David J ; OLDIGES, Philip ; CHUANG, Ching-Te ; ROY, Kaushik |
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Zeitschrift: | IEEE electron device letters, Jg. 27 (2006), Heft 4, S. 284-287 |
Veröffentlichung: | New York, NY: Institute of Electrical and Electronics Engineers, 2006 |
Medientyp: | academicJournal |
Umfang: | print, 17 ref |
ISSN: | 0741-3106 (print) |
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